1. Field of the Invention
The present invention relates to a failure counting method and device for calculating the number of defective memory cells (the number of failures) used in the failure analysis of a semiconductor memory.
2. Description of the Related Art
A semiconductor memory testing device that tests a semiconductor memory is provided with a failure analysis memory for storing failure data, which are the pass/fail determination results of each memory cell of a semiconductor memory. The failure data stored in the failure analysis memory is processed by a failure counter incorporated in the semiconductor memory testing device, the number of memory cell failures is calculated, and these results are used in judging whether an article passes or fails, or are used in a prescribed application of the semiconductor memory testing device.
In a prior-art failure counting method that seeks the number of failures of memory cells using such a failure analysis memory, a failure counter is provided with a pattern generator that generates addresses in order, the output of the pattern generator is impressed to the failure analysis memory, all addresses of the failure analysis memory are scanned, each of the stored failure data are read out, and the number of data items "1" indicating "fail" among the read failure data are counted.
In a case in which the failure analysis memory is a semiconductor memory of multi-bit structure capable of reading and writing in units of a plurality of bits, addresses are impressed for every unit of a plurality of bits, and the content of this plurality of bits is read at once in one scan.
In the above-described failure counting method of the prior art, however, the memory capacity of the failure analysis memory that employs high-cost memory such as SRAM(Static RAM) has increased along with the increase in the memory capacity of semiconductor memory, which is the object of testing, resulting in the drawbacks of prolonged processing time and increased cost of components of the semiconductor memory testing device.
To reduce the processing time, a method of finding the number of failures can be considered wherein, for example, the data storage region of the failure analysis memory is divided into a plurality of regions, whereby the failure data of these regions that are simultaneously scanned and read can be processed in parallel to find the number of failures.
However, in prior-art methods in which all addresses are scanned by a pattern generator, parallel processing is prevented because failure data for each region cannot be read simultaneously, and this inability interferes with reducing processing time.